High-density modern semiconductor processes allow designers to shrink what would have been a board-level system into just a single system-on-a-chip (SOC) integrated circuit. As part of this integration, memories that would have existed as separate integrated circuits become embedded memories within a SOC. Although the resulting integration provides a very compact design, the testing of SOCs becomes more and more challenging as the number of integrated components rises. This testing may be classified into two categories, namely that of testing logic and testing memory. Testing embedded memories, such as SRAM's, is more difficult than testing dedicated memory chips because of the relative inaccessibility of the embedded memory. This testing difficulty manifests itself in several ways, such as in memory writing, memory reading, and the memory data path width to the input/output (IO) facilities of the integrated circuit. Should the embedded memories be used as read-only memory (ROM), a user will also need to configure the memories before operation of the integrated circuit. The need to configure and test embedded memories exacerbates the already considerable die area demands of embedded memories.
Conventional approaches for testing embedded memories have included the use of on-chip hardware such as a built-in-self-test (BIST) engine. In a BIST engine, a BIST controller generates test patterns (typically denoted as test vectors) that are written to and read back from the embedded memories. The originally-written test vectors are compared to the read test vectors so that errors in the embedded memories may be identified. Although testing embedded memories with BIST engines is relatively fast, the BIST engine occupies substantial die area and hence raises the die cost. Moreover, the test patterns are limited to whatever patterns the BIST engine has been designed to generate, thereby limiting the resulting fault coverage as well as the failure analysis. Finally, the BIST engine itself could be faulty, thus lowering manufacture yield and increasing costs.
An alternative to the on-chip BIST engine embedded memory testing approach is the use of conventional external testers. These external testers generate the test vectors that make up the test pattern that is written to the embedded memory. In such an approach, the die demands from an on-chip BIST engine is eliminated. Moreover, the external tester has greater flexibility in the variety of test patterns/test vectors that may be generated. However, the external tester must retrieve the written test vectors that comprise a given test pattern from the embedded memory being tested and compare the retrieved test vectors to the expected values for the retrieved test vectors. To limit output pin demands, the retrieved data words are typically shifted off chip in a serial fashion. Accordingly, external testing approaches are necessarily slower than on-chip BIST engine implementations.
Accordingly, there is a need in the art for improved testing and configuration capabilities for embedded memories.